The present disclosure relates generally to systems and methods that counteract aging effects due to negative-bias temperature instability.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
An electronic device may transmit and receive data between various internal components as well as to other electronic devices based on rising and/or falling edges of clock signals. The circuitry of the electronic device that transmits or receives the data may depend on a relatively stable duty cycle for proper operation. For example, a signal may have a duty cycle of 50% in which the signal may be in a HIGH logic state (e.g., 1) for half of the signal period and in a LOW logic state (e.g., 0) for the other half of the signal period. Signals that are in a HIGH logic state for more than half of the signal period have a duty cycle above 50%, while signals that are in a LOW logic state for more than half of the signal period have duty cycles below 50%. It should be noted that different circuitry may specify different duty cycles; while a 50% duty cycle may be specified for certain types of circuitry, other duty cycles may be used by other types of circuitry.
Many high-speed circuits use both the rising and the falling edges of a clock signal for timing. Circuits that rely on both the rising and the falling edges of a signal include double-data-rate (DDR) circuitry, as well as half-rate clock and data recovery (CDR) circuits. These circuits could be subject to aging due to prolonged periods of time where one particular state of the signal is applied for an extended period of time. For example, longer periods of a LOW logic state that occurs when the clock signal is disabled may age the circuit to in a way that causes the duty cycle to be distorted in a particular way. When this occurs, a desired duty cycle (e.g., 50%) may become distorted to operate at higher than or lower than 50%. Aging in which the duty cycle tends towards the state of the signal after prolonged exposure to that state may be referred to as negative-bias temperature instability.